In many (high-speed) analog-to-digital converters (ADCs), the analog input-signal is sampled onto input sampling-capacitors prior to conversion. Any intervening circuitry between the analog input and the sampling capacitors can be a source of degradation, adding distortion and/or noise. Therefore, to achieve the highest possible spurious-free-dynamic-Range (SFDR) and highest Signal-to-Noise-Ratio (SNR), many high-performance samplers and ADCs leave out active front-end differential amplifiers, resulting in topologies similar to those shown in FIG. 1. FIG. 1a shows a conventional op-amp based design, and FIG. 1b shows Kenet's Common-gate-charge-pipeline sampling front-end (covered by other patents). Note how both approaches employ the same switch-capacitor network attached to the analog inputs, with similarly timed clocking. The rest of this description will be based on results obtained with Kenet's Common-gate-charge-pipeline, but the unique features of the disclosed sampler could be applied equally well to the conventional approach.
While a single-ended sampler/converter can be made from the circuits shown in FIG. 1, more commonly, a pair of single-end samplers/converters are mated together to form a differential configuration, as shown in FIG. 2. (Operation of the sampler/converter input circuitry is illustrated in FIGS. 3 and 4, showing the two primary clock phases, track and hold). The circuits are mirrored about the horizontal center-line, creating m (minus) and p (plus) halves of the sampler/converter. Ideally, a differential signal, vdiff, is applied to the vinp and vinm inputs, centered about some common-mode value, Vcm, i.e., Vinp=Vcm+vdiff/2, Vinm=Vcm−vdiff/2.
In practice, most analog inputs, even those intended to be fully differential, have some residual common-mode voltage variation as the differential-signal swings through its range. For example, the inputs of high-speed converters are often driven from transformer-based baluns that perform unbalanced (single-ended) to balanced (differential) conversion. These baluns are not perfect, resulting in a common-mode component at their outputs. Another way to say this is that if vinp and vinm do not have equal amplitudes and exactly 180° relative-phase, a residual time-varying common-mode component will appear at the sampler/converter inputs. The sampler converts input voltage to charge stored on the sampling capacitors, so any input common-mode-voltage variation will result in a common-mode charge variation on the two sampling capacitors. Downstream circuitry must then be able to accommodate this common-mode variation without a loss in performance.
A second approach to driving the converter inputs is to precede the converter with an active differential amplifier, as mentioned above. This differential amplifier can provide some degree of common-mode rejection, like the transformer. But again, real-life amplifiers are not perfect, and they too leave a residual common-mode voltage variation for the sampler/converter to deal with. Additionally, these active amplifiers add distortion and noise, often exceeding that of the sampler/converter itself.